1. Field of the Invention
The present invention relates to a manufacturing method of shallow trench isolation for semiconductor integrated circuits and more particularly to a method by depositing SiON anti-reflective layers with different extinction coefficient (k) to decrease the effect on exposure of the silicon nitride (Si3N4) and control the width of the window, then the critical dimension (CD) of the active area can be controlled and the filling capability can be improved.
2. Description of Relative Prior Art
The manufacturing technology of integrated circuit is developing smaller and smaller according to Moore's law. The size of a chip is also continuously decreasing because of the increasing of integrity to increase the device number per unit area of a chip. The critical dimension of semiconductor is shrinking from sub-micron to nanometer (nm). Most of the exposure light source is 248 μm, even 193 μm of wave length for increasing resolution. As the dimension of devices is decreased, it still needs isolation from each other. Isolation technology has developed from LOCOS technology to shallow trench isolation (STI). STI has the advantages of small isolation area and better planarization, especially by using chemical mechanical polishing (CMP) technology, the planarization become more ideal. The traditional STI technology is shown in FIG. 1. FIG. 1 is the cross sectional view of STI process. First, a layer of pad oxide 102 is grown on a silicon substrate 101, a layer of silicon nitride 103 is deposited on said pad oxide 102; Then, as shown in FIG. 1B, a designated thickness of silicon oxy-nitride (SiON) 104 is deposited, in FIG. 1C, using a STI mask to expose the photo-resist for etching the trench. However, the extinction coefficient of the silicon oxy-nitride is nearly zero under the 248 μm or 193 μm exposure light source, so the reflectivity of SiON 104 is easily affected by the thickness variation of the silicon nitride layer 103 under it, and the opening or window of the photo-resist 105 is not enough after developed, and the critical dimension of ADI (after development inspection) has too much variation, the critical dimension of the active area (AA) can not be controlled. This will affect the performance and yield of the chip. After refilling of silicon dioxide layer 107 into the trench, planarization becomes worse because of high aspect ratio. This also formed voids 108, which will affect isolation capability, as shown in FIG. 1E.
FIG. 2 shows the reflectivity 201 versus the thickness of Si3N4 103 with a normal SiON on the Si3N4. From curve 201 of FIG. 2, the reflectivity has a minimum of 0.025 for a thickness of 930 Å of silicon nitride 103. The reflectivity is increasing linearly with increasing thickness of the silicon nitride 103. Thus the thickness of silicon nitride affects the reflectivity, and that a normal SiON can not be effectively used as anti-reflected material. After development inspection, the CD will be changed, results a variable trench width after etching, and will have not enough width of the opening.
The curve 301 in FIG. 3 shows the ADI size for different thickness of silicon nitride 103. From curve 301 of FIG. 3, for a silicon nitride thickness of 910 Å, the ADI size is 0.146 μm; for a silicon nitride thickness of 950 Å, the ADI size is 0.16 μm. Therefore, if the thickness between wafer to wafer or within a wafer is not uniform, the ADI for different wafers or different position of a wafer will not be the same, and is then affect the performance of devices or yield of the product.